Personal computing devices such as portable wireless telephones and personal digital assistants (PDAs) are requiring ever-increasing data storage capacity to perform a continuously wider scope of applications. For example, a wireless telephone can include a digital video camera, video and audio file player, portable game player, and Internet access/web browser. Concurrent with the requirement for handling a wider scope of applications, battery life is highly valued and, therefore, power consumption by the data storage is preferably kept to a minimum.
Resistance-memories, which store data as a switchable resistance, show promise for meeting anticipated storage needs in applications such as personal computing devices. One type of resistance memory, spin transfer torque (STT) magnetic tunneling junction (MTJ), or STT-MTJ shows particular promise. STT-MTJ has high read/write access speed, is compatible with MOS processing, and has very high cycle endurance. In brief, an STT-MTJ cell includes a fixed magnetic layer and a free magnetic layer, each having magnetic domains. The alignment of the free magnetic layer domains relative to the fixed magnetic layer domains can be switched into one of two stable states, parallel (P) and anti-parallel (AP). One of the P and AP states may represent a binary “0” and the other a binary “1.” The electrical resistance of the STT-MTJ in the P state is lower than its resistance in the AP state. An STT-MTJ cell may therefore be read by detecting its resistance.
The conventional means for reading an STT-MTJ cell is by passing a read current through it and comparing, by a sensing amplifier, the resulting “read” voltage to a reference voltage. For read accuracy, the reference voltage is ideally halfway between the “0” voltage and the “1” voltage. To provide a reference voltage at this desired halfway point a reference current, ideally having the same magnitude as the read current, is passed through a parallel arrangement of a reference STT-MTJ programmed at “0” state and a reference STT-MTJ programmed at a “1” state. Ideally the reference STT-MTJs have P and AP state resistances identical to the P and AP state resistances of the actual storage STT-MTJs. Therefore, assuming the reference current and read current have the same magnitude, this generates a reference voltage at the ideal point, halfway between the “0” voltage and the “1” voltage.
In a conventional magnetic random access memory (MRAM) formed as an m column by n row array of STT-MTJ cells, one sensing amplifier may be provided for each of every L columns (e.g., four, six, eight), and a reference circuit may be provided for feeding a reference voltage line that connects to one of the inputs of the sensing amplifiers.
For read accuracy and access speed, a general design goal is having both the reference voltage and the read voltage reach an acceptably steady state at the inputs of the sensing amplifier as quickly as possible. However, in a conventional magnetic random access memory (MRAM) formed of STT-MTJ cells the path through which the reference current flows has a significantly different structure and arrangement, and different electrical characteristics as compared to the path through which the read current flows. The differences in electrical characteristic may include significant differences in their respective loads. Further, the path for the reference current and the path for the read current may have substantially different structure, and therefore variances in their respective physical parameters due to fabrication tolerances may cause a corresponding large variance in the difference between their electrical characteristics, and hence their different delay. A result may be a corresponding significant variance in read access timing.
A need has therefore existed in the MRAM arts for fast arrival of stable, accurate read voltages and reference voltage at inputs of read sensing amplifiers, as well as other performance and yield-increasing improvements.